Integrated circuits are formed on a semiconductor substrate, which is typically composed of silicon. Such formation of integrated circuits involves sequentially forming or depositing multiple electrically conductive and insulative layers in or on the substrate. Etching processes may then be used to form geometric patterns in the layers or vias for electrical contact between the layers. Etching processes include “wet” etching, in which one or more chemical reagents are brought into direct contact with the substrate, and “dry” etching, such as plasma etching.
Various types of plasma etching processes are known in the art, including plasma etching, reactive ion (RI) etching and reactive ion beam etching. In each of these plasma processes, a gas is first introducted into a reaction chamber and then plasma is generated from the gas. This is accomplished by dissociation of the gas into ions, free radicals and electrons by using an RF (radio frequency) generator, which includes one or more electrodes. The electrodes are accelerated in an electric field generated by the electrodes, and the energized electrons strike gas molecules to form additional ions, free radicals and electrons, which strike additional gas molecules, and the plasma eventually becomes self-sustaining. The ions, free radicals and electrons in the plasma react chemically with the layer material on the semiconductor wafer to form residual products which leave the wafer surface and thus, etch the material from the wafer.
Referring to the schematic of FIG. 1, a conventional plasma etching system, such as an Mxp+ Super-E etcher available from Applied Materials, Inc., is generally indicated by reference numeral 10. The etching system 10 includes a reaction chamber 12 having a typically grounded chamber wall 14. An electrode, such as a planar coil electrode 16, is positioned adjacent to a dielectric plate 18 which separates the electrode 16 from the interior of the reaction chamber 12. Plasma-generating source gases are provided by a gas supply (not shown). Volatile reaction products and unreacted plasma species are removed from the reaction chamber 12 by a gas removal mechanism, such as a vacuum pump 24 through a throttle valve 26.
The dielectric plate 18 illustrated in FIG. 1 may serve multiple purposes and have multiple structural features, as is well known in the art. For example, the dielectric plate 18 may include features for introducing the source gases into the reaction chamber 12, as well as those structures associated with physically separating the electrode 16 from the interior of the chamber 12.
Electrode power such as a high voltage signal is applied to the electrode 16 to ignite and sustain a plasma in the reaction chamber 12. Ignition of a plasma in the reaction chamber 12 is accomplished primarily by electrostatic coupling of the electrode 16 with the source gases, due to the large-magnitude voltage applied to the electrode 16 and the resulting electric fields produced in the reaction chamber 12. Once ignited, the plasma is sustained by electromagnetic induction effects associated with time-varying magnetic fields produced by the alternating currents applied to the electrode 16. The plasma may become self-sustaining in the reaction chamber 12 due to the generation of energized electrons from the source gases and striking of the electrons with gas molecules to generate additional ions, free radicals and electrons. A semiconductor wafer 34 is positioned in the reaction chamber 12 and is supported by a wafer platform or ESC (electrostatic chuck) 36. The ESC 36 is typically electrically-biased to provide ion energies that are independent of the RF voltage applied to the electrode 16 and that impact the wafer 34.
Typically, the voltage varies as a function of position along the coil electrode 16, with relatively higher-amplitude voltages occurring at certain positions along the electrode 16 and relatively lower-amplitude voltages occurring at other positions along the electrode 16. A relatively large electric field strength is required to ignite plasmas in the reaction chamber 12. Accordingly, to create such an electric field it is desirable to provide the relatively higher-amplitude voltages at locations along the electrode 16 which are close to the grounded chamber wall 14.
As discussed above, plasma includes high-energy ions, free radicals and electrons which react chemically with the surface material of the semiconductor wafer to form reaction produces that leave the wafer surface, thereby etching a geometrical pattern or a via in a wafer layer. Plasma intensity depends on the type of etchant gas or gases used, as well as the etchant gas pressure and temperature and the radio frequency generated at the electrode 16. If any of these factors changes during the process, the plasma intensity may increase or decrease with respect to the plasma intensity level required for optimum etching in a particular application. Decreased plasma intensity results in decreased, and thus incomplete, etching. Increased plasma intensity, on the other hand, can cause overetching and plasma-induced damage of the wafers. Plasma-induced damage includes trapped interface charges, material defects migration into bulk materials, and contamination caused by the deposition of etch products on material surfaces. Etch damage induced by reactive plasma can alter the qualities of sensitive IC components such as Schottky diodes, the rectifying capability of which can be reduced considerably. Heavy-polymer deposition during oxide contact hole etching may cause high-contact resistance.
FIG. 2 illustrates structural details of the environment of the ESC 36 inside the reaction chamber 12. A typically silicon insert ring 40 is interposed between a shadow ring 38 and the outer circumference of the ESC 36. The insert ring 40 enhances uniformity of the etch rate among all areas on the surface of the wafer 34. A gap 46 (known in the art as a berline wall) is defined between the flat inner edge 42 of the insert ring 40 and the outer circumference of the ESC 36. The edge of the wafer 34, resting on the ESC 36, may extend over the gap 46.
As shown in FIG. 3, throughout repeated processing of successive wafers 34 on the ESC 36, a deposit of polymer material 44 tends to gradually accumulate on the outer edge of the ESC 36, and extends into the gap 46. This deposit of polymer material 44 gradually grows and closes or substantially narrows the gap 46, finally becoming deposited on the flat inner edge 42 of the insert ring 40. This renders non-uniform the leakage of cooling helium to the backside of the wafer 34 during etching, thereby energizing the B/H alarm of the etching system between PM (periodic maintenance) cycles.
Furthermore, accumulation of the polymer material 44 onto the insert ring 40 causes peeling of polymer particles from the ESC 36 and the insert ring 40. These polymer particles can potentially contaminate devices being formed on the wafers 34. Consequently, the ESC 36 and the insert ring 40 must be wet-cleaned about every 70 hours of operation of the system 10.
One of the approaches which has been taken to retard the accumulation of the polymer deposit 44 on the insert ring 40 has included widening or narrowing of the gap 46. However, this tends to increase deposition of the polymer deposit 44 on, and accelerate polymer peeling from, the insert ring 40. Furthermore, in the case of an insert ring 40 having a flat upper surface, the gap 46 provides a “straight line” path for plasma species 48 to flow between the ESC 36 and the flat inner edge 42 of the insert ring 40, as shown in FIG. 2.
It has been found that providing a stepped profile to the insert ring provides a “perpendicular flow” path for plasma species in the gap between the ESC and the edge of the insert ring. This stepped profile substantially hinders flow of the plasma species into the gap and substantially reduces the rate of polymer deposition onto the ESC sidewall.
It is therefore an object of the present invention to provide a novel insert ring for a wafer support, which insert ring prevents or minimizes the formation of polymer material thereon during processing of wafers on the support.
Another object of the present invention is to provide a novel wafer support insert ring having a stepped cross-sectional configuration to prevent or at least minimize the formation of polymer material between the ring and a wafer support or ESC that supports a wafer during an etching process.
Still another object of the present invention is to provide a novel wafer support insert ring having a stepped cross-sectional configuration to impart a perpendicular flow path of plasma species between the inner surface of the ring and a wafer support and prevent or minimize the formation of polymer material between the ring and ESC during an etching process.
Another object of the present invention is to provide a novel wafer support insert ring having a stepped cross-sectional configuration to reduce deposit of polymer material on the sidewall of a wafer support and increase utilization of an etcher.
Yet another object of the present invention is to provide a novel wafer support insert ring which prevents or minimizes the quantity of polymer material capable of accumulating in a gap between the innner surface of the insert ring and the exterior circumference of an electrostatic chuck (ESC) or other wafer support in a process chamber.
A still further object of the present invention is to provide a novel wafer support insert ring which extends the time between periodic maintenance or cleanings required for an etching chamber.
Yet another object of the present invention is to provide a novel wafer support insert ring which prevents or substantially reduces polymer peeling in a process chamber for semiconductor wafer substrates.